Semiconductor memories include a DRAM (Dynamic Random Access Memory) which is capable of high speed data rewriting. Along with progress in ultra large scale integration technology, the DRAM has entered a large capacity range of 256 M to 1 G bit. Therefore, there has been a demand for integration of circuits; and, more particularly, the size of capacitors for storing information has been made finer. Means for effecting the integration of capacitors can include reduction in the film thickness of dielectrics, selection of materials of high dielectric constant and a three-dimensional structure comprising top and bottom electrodes and a dielectric.
Among these choices, for the dielectric material, it has been known that BST having a single unit cell of perovskite structure ((Ba/Sr)TiO3) as the crystal structure has higher dielectric constant (∈) compared with SiO2/Si3N4. An example of using high dielectric materials has been reported in Japan Journal of Applied Physics, 1995, 5077p (Jpn. J. Appl. Phys., 34, 5077, 1995). According to this report, since the condition for the aspect ratio (contact hole patterns of 800 nm depth/240 nm diameter) of a three-dimensional structure using BST is about 0.65, top and bottom electrodes and a dielectric are prepared by a sputtering method.